The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

May. 29, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Cheng Long Zhang, Shanghai, CN;

Hai Yang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/5283 (2013.01); H01L 23/53257 (2013.01); H01L 29/41791 (2013.01); H01L 21/76834 (2013.01); H01L 27/1211 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes an active region having a doped region, a first contact member on the doped region, gate structures including a first gate structure having a first gate and a second gate structure having a second gate, the first and second gate structures being adjacent to each other and on opposite sides of the first contact member, an interlayer dielectric layer on the active region and surrounding the first and second gate structures, and the first contact member, a first insulator layer on a portion of the interlayer dielectric layer, a first contact on an upper surface of the first gate and a second contact on an upper surface of the second gate, and a second insulator layer surrounding the first and second contacts each having an upper surface lower than an upper surface of the second insulator layer.


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