The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Jul. 31, 2018
Applicant:

Ablic Inc., Chiba-shi, Chiba, JP;

Inventors:

Yuki Osuga, Chiba, JP;

Hirofumi Harada, Chiba, JP;

Mio Mukasa, Chiba, JP;

Assignee:

ABLIC INC., Chiba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/861 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 29/42336 (2013.01); H01L 29/66712 (2013.01); H01L 29/66734 (2013.01); H01L 29/7804 (2013.01); H01L 29/7813 (2013.01); H01L 29/861 (2013.01); H01L 29/4983 (2013.01);
Abstract

Provided is a semiconductor device having an ESD protection diode and a vertical MOSFET in which desired ESD tolerance is obtained without reducing the active region size or increasing the chip size. The semiconductor device includes: a substrate; a drain region and a source region in the substrate; a base region between the drain region and the source region; a gate electrode comprising a first polysilicon layer, and being in contact with the base region across a gate insulating film so that a channel is formed in the base region; and a bidirectional diode in which the gate electrode, a second polysilicon layer, and a third polysilicon layer are arranged in the stated order in a direction perpendicular to a front surface of the substrate.


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