The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Aug. 10, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Cheng Long Zhang, Shanghai, CN;

Qi Yang He, Shanghai, CN;

Yan Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/528 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/0276 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76816 (2013.01); H01L 21/76843 (2013.01); H01L 21/76865 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01);
Abstract

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region. The base substrate includes a base interconnection structure. The method also includes forming a medium layer on the base substrate. In addition, the method includes forming a first trench having a first depth in the peripheral region, and forming a second trench having a second depth in the device region. The second depth is greater than the first depth. Moreover, the method includes forming a first opening in the device region and forming a second opening in the peripheral region. Further, the method includes forming a first interconnection structure by filling the first opening with a conductive material and forming a second interconnection structure by filling the second opening with the conductive material.


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