The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Dec. 14, 2017
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Andrew M. Greene, Albany, NY (US);
Ekmini Anuja De Silva, Slingerlands, NY (US);
Siva Kanakasabapathy, Pleasanton, CA (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/28247 (2013.01); H01L 21/32139 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract
Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.