The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Nov. 28, 2018
Applicant:
Imec Vzw, Leuven, BE;
Inventors:
Amey Mahadev Walke, Heverlee, BE;
Nadine Collaert, Blanden, BE;
Assignee:
IMEC VZW, Leuven, BE;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 23/535 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/823871 (2013.01); H01L 21/84 (2013.01); H01L 23/535 (2013.01); H01L 27/0694 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 27/0207 (2013.01);
Abstract
Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.