The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Dec. 18, 2017
Applicant:

Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, CN;

Inventor:

Jian Hu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/16 (2006.01); G11C 11/56 (2006.01); H01L 29/423 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 27/11517 (2017.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 11/5642 (2013.01); G11C 16/0425 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 29/42324 (2013.01); G11C 11/5635 (2013.01); H01L 27/11517 (2013.01);
Abstract

A memory array and a method for reading, programming and erasing the same are provided. The memory array includes flash memory cells arranged in an array, each flash memory cell includes a first and a second split-gate flash memory cell; a first control gate of the first split-gate flash memory cell is connected with a first control gate of the second split-gate flash memory cell and a first control gate line, a second control gate of the first split-gate flash memory cell is connected with a second control gate of the second split-gate flash memory cell and a second control gate line; a word line gate of the first split-gate flash memory cell is connected with a word line gate of the second split-gate flash memory cell and a word line; two drains of the first and second split-gate flash memory cells share a same bit line.


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