The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Apr. 02, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Amitabha Roy, Santa Clara, CA (US);

Subramanya R. Dulloor, Santa Clara, CA (US);

Rajesh M. Sankaran, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 12/0831 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 12/1027 (2013.01); G06F 2212/621 (2013.01); G06F 2212/68 (2013.01);
Abstract

Methods and apparatuses relating to memory performance monitoring are described, including a processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions. In one embodiment, a processor includes at least one core, a performance monitoring unit, and a memory management unit including a first allocator to allocate a first virtual memory region of a memory for a first data structure, and a second allocator to allocate a second, different virtual memory region of the memory for a second data structure, wherein the memory management unit is to enable the performance monitoring unit to monitor a memory access request from the at least one core when a monitor flag is set for the first virtual memory region or the second, different virtual memory region, and a translation lookaside buffer (TLB) comprising a protection key for a page of a page table, wherein the is to translate a virtual address of the memory access request to a physical address and to set the monitor flag when the page includes the virtual address of the memory access request and the protection key indexes into a key register that indicates the virtual address of the memory access request is to be monitored, wherein the memory management unit is to append the monitor flag to the physical address.


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