The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Jul. 19, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Karthikeyan Avudaiyappan, Sunnyvale, CA (US);
Mohammad Abdallah, El Dorado Hills, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2016.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0804 (2013.01); G06F 12/0815 (2013.01); G06F 12/0897 (2013.01); G06F 12/12 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/283 (2013.01); G06F 2212/608 (2013.01);
Abstract
A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.