The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Mar. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Francesc Guim Bernat, Barcelona, ES;

Thomas Willhalm, Sandhausen, DE;

Karthik Kumar, Chandler, AZ (US);

Martin P. Dimitrov, Chandler, AZ (US);

Raj K. Ramanujan, Federal Way, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/0815 (2013.01); G06F 2212/621 (2013.01); Y02D 10/154 (2018.01);
Abstract

Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.


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