The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Jun. 12, 2018
Nxp Usa, Inc., Austin, TX (US);
Robert S. Jones, III, Austin, TX (US);
Xiankun Jin, Austin, TX (US);
NXP USA, INC., Austin, TX (US);
Abstract
A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit. A first terminal of the second variable resistor circuit is coupled to a first test port and a second terminal of the second variable resistor circuit is coupled to a second test port to allow for a resistance measurement of the second variable resistor circuit during a test mode. The current source circuit includes a non-volatile storage circuit configured to store a tap value generated during the test mode corresponding to a set of select signal values for the second plurality of tap inputs which provides a desired resistance of the second variable resistor circuit as determined during the test mode and to provide a set of select signal values for the first plurality of tap inputs based on the tap value stored in the non-volatile storage circuit.