The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Dec. 28, 2016
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Sarit Zur, Petah-Tikva, IL;

Ofer Benjamin, Petach-Tikva, IL;

Eshel Gordon, Aloney Aba, IL;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 7/02 (2006.01); H04B 1/00 (2006.01); H04B 1/16 (2006.01); H04K 3/00 (2006.01); H04W 16/14 (2009.01); H04W 84/12 (2009.01);
U.S. Cl.
CPC ...
H04B 1/001 (2013.01); H04B 1/1607 (2013.01); H04K 3/822 (2013.01); H04W 16/14 (2013.01); G01S 7/021 (2013.01); G01S 7/023 (2013.01); H04K 3/226 (2013.01); H04W 84/12 (2013.01);
Abstract

An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.


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