The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Dec. 07, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hao Wang, San Diego, CA (US);

Haining Yang, San Diego, CA (US);

Xiaonan Chen, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7391 (2013.01); H01L 27/0255 (2013.01); H01L 29/083 (2013.01); H01L 29/0834 (2013.01); H01L 29/66356 (2013.01); H01L 29/0847 (2013.01); H01L 29/495 (2013.01); H01L 29/7851 (2013.01);
Abstract

Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.


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