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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10340177 B1

PDFFull Text
Date of Patent:
Jul. 02, 2019

Filed:

Feb. 19, 2016

Devices and methods of reducing damage during beol m1 integration

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ashwini Chandrashekar, Clifton Park, NY (US);

Anbu Selvam Km Mahalingam, Malta, NC (US);

Craig Michael Child, Jr., Gansevoort, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorneys:

Thompson Hine LLP

Francois Pagette

Primary Examiner:

Zandra V Smith

Assistant Examiner:

Andre′ C Stevenson

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/00 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/0214 (2013.01); H01L 21/02126 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/53295 (2013.01);
Abstract

Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

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