The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Mar. 27, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Katsuhiro Kitagawa, Hachioji, JP;

Kazuhiro Kurihara, Setagaya-ku, JP;

Kohei Nakamura, Fuchu, JP;

Akira Yamashita, Sagamihara, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); H03K 5/1534 (2006.01); H03K 5/05 (2006.01); H03K 3/037 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); H03K 3/037 (2013.01); H03K 5/05 (2013.01); H03K 5/135 (2013.01); H03K 5/1534 (2013.01); H03K 2005/00286 (2013.01);
Abstract

Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.


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