The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Dec. 01, 2016
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Ankit Jindal, Pune, IN;

Pranavkumar Sawargaonkar, Pune, IN;

Keyur Chudgar, San Jose, CA (US);

Assignee:

Ampere Computing LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 3/06 (2006.01); G06F 12/109 (2016.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 3/067 (2013.01); G06F 3/0664 (2013.01); G06F 12/109 (2013.01); G06F 12/1425 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/152 (2013.01); G06F 2212/154 (2013.01);
Abstract

Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.


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