The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Aug. 21, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Shogo Mochizuki, Schenectady, NY (US);

Jie Yang, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/26513 (2013.01); H01L 29/0847 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.


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