The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Dec. 30, 2013
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Harry Hak-Lay Chuang, Singapore, SG;

Wei-Cheng Wu, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 27/11531 (2017.01); H01L 27/06 (2006.01); H01L 27/108 (2006.01); H01L 27/11575 (2017.01); H01L 27/11568 (2017.01); H01L 29/792 (2006.01); H01L 27/11526 (2017.01); H01L 29/66 (2006.01); H01L 27/11521 (2017.01); H01L 27/105 (2006.01); H01L 23/525 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 27/11531 (2013.01); H01L 27/11573 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 21/823437 (2013.01); H01L 23/5256 (2013.01); H01L 27/0629 (2013.01); H01L 27/1052 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11568 (2013.01); H01L 27/11575 (2013.01); H01L 29/66545 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (STI) region, a protective structure located on the STI region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a process of the high-k dielectric layer deposited before the formation of the first and second semiconductor structures.


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