The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Jun. 24, 2014
Applicant:

Imec, Leuven, BE;

Inventors:

Eric Beyne, Leuven, BE;

Wenqi Zhang, Leuven, BE;

Geraldine Jamieson, Balen, BE;

Bart Swinnen, Holsbeek, BE;

Assignee:

IMEC, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 21/4853 (2013.01); H01L 23/49811 (2013.01); H01L 24/03 (2013.01); H01J 2237/334 (2013.01); H01J 2237/338 (2013.01); H01J 2237/3342 (2013.01); H01J 2237/3347 (2013.01); H01J 2237/3348 (2013.01); H01J 2237/3382 (2013.01); H01L 2224/03466 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0601 (2013.01); H01L 2224/16237 (2013.01);
Abstract

Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.


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