The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Nov. 22, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuang-Hsiu Chen, Tainan, TW;

Hsu Ting, Tainan, TW;

Chung-Fu Chang, Tainan, TW;

Shi-You Liu, Kaohsiung, TW;

Chun-Wei Yu, Tainan, TW;

Yu-Ren Wang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3105 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/165 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3105 (2013.01); H01L 21/02532 (2013.01); H01L 21/266 (2013.01); H01L 21/26533 (2013.01); H01L 21/26586 (2013.01); H01L 21/324 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.


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