The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Dec. 21, 2017
Applicants:

Imec Vzw, Leuven, BE;

Vrije Universiteit Brussel, Brussels, BE;

Inventors:

Trong Huynh Bao, Leuven, BE;

Julien Ryckaert, Schaerbeek, BE;

Praveen Raghavan, Leefdaal, BE;

Pieter Weckx, Bunsbeek, BE;

Assignees:

IMEC vzw, Leuven, BE;

Vrije Universiteit Brussel, Brussels, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); H01L 27/11 (2006.01); H01L 29/423 (2006.01); G11C 11/408 (2006.01); H01L 29/08 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/4085 (2013.01); H01L 27/0688 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01);
Abstract

In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.


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