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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10331838 B1

PDFFull Text
Date of Patent:
Jun. 25, 2019

Filed:

Jul. 26, 2017

Semiconductor device with fill cells

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jung-Chan Yang, Taoyuan, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Ting-Wei Chiang, New Taipei, TW;

Yun-Xiang Lin, Hsinchu County, TW;

Tien-Yu Kuo, Hsinchu, TW;

Shu-Yi Ying, Hsinchu County, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Maschoff Brennan

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/77 (2017.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); H01L 21/77 (2013.01); G06F 2217/12 (2013.01); Y02P 90/265 (2015.11);
Abstract

A layout method is disclosed that includes: placing function cells in a layout, corresponding to at least one design file, of an integrated circuit; and inserting at least one fill cell that is configured without cut pattern to fill at least one empty region between the function cells each comprising at least one cut pattern on at least one edge abutting the at least one empty region.

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Yang, Jung-Chan. (2019). Semiconductor device with fill cells (U.S. Patent No. 10331838). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10331838

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