The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Sep. 06, 2018
Applicant:

Synopsys, Inc., Mountian View, CA (US);

Inventors:

Johnson Adaikalasamy, Sunnyvale, CA (US);

Gagan Vishal Jain, Sunnyvale, CA (US);

Stanislav Margolin, Andover, MA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5027 (2013.01); G06F 17/5031 (2013.01); G06F 2217/84 (2013.01);
Abstract

A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.


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