The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Apr. 13, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Aman Bhatia, San Jose, CA (US);

June Lee, Sunnyvale, CA (US);

Chenrong Xiong, San Jose, CA (US);

Naveen Kumar, San Jose, CA (US);

Fan Zhang, Fremont, CA (US);

Yu Cai, San Jose, CA (US);

Assignee:

SK Hynix Inc, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); H03M 13/11 (2006.01); G06F 11/10 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1108 (2013.01); G06F 11/1072 (2013.01); G06F 11/3034 (2013.01); G06F 11/3409 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); H03M 13/611 (2013.01);
Abstract

Techniques for processing bits associated with an 'N' multiple level cell NAND flash memory, such as a QLC NAND flash memory, are described. In an example, a system generates a symbol based on the bits. The symbol corresponds to at least two bits. The system encodes the symbol in a non-binary codeword and stores the non-binary codeword in the 'N' multiple level cell NAND flash memory based on a mapping between symbols and voltage levels of the “N” multiple level cell NAND flash memory. The system initializes a non-binary decoding procedure based on asymmetric crossover probabilities between the voltage levels. The asymmetric crossover probabilities are defined based on the mapping between the symbols and the voltage level. The system decodes the non-binary codeword based on the non-binary decoding procedure.


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