The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Oct. 08, 2014
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Sheng Fen Chiu, Shanghai, CN;

Fansheng Kung, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 21/3205 (2006.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28247 (2013.01); H01L 21/28273 (2013.01); H01L 21/76897 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 21/26513 (2013.01); H01L 21/32134 (2013.01); H01L 21/32137 (2013.01); H01L 29/4916 (2013.01);
Abstract

Various embodiments provide memory devices and methods for forming the same. In an exemplary method, a provided substrate has one or more memory cells, a memory cell of which includes a control gate layer. The control gate layer has a first portion and a second portion on the first portion. A silicide layer is formed in the control gate layer and covers at least a sidewall of the second portion. A portion of the silicide layer is removed to reduce a size of the silicide layer in a direction parallel to the substrate. A fourth dielectric layer is formed on the substrate and on the memory cell, and has a top surface higher than a top surface of the memory cell. An opening is formed in the fourth dielectric layer and exposes a portion of the substrate between adjacent memory cells. A conductive structure is formed in the opening.


Find Patent Forward Citations

Chiu, Sheng. (2019). Memory device and method for forming the same (U.S. Patent No. 10325916). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10325916

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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