The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Jan. 04, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Liang Han, Shanghai, CN;

Sheng Fen Chiu, Shanghai, CN;

Liang Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); H01L 21/82 (2006.01); H01L 27/11519 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); H01L 21/28273 (2013.01); H01L 27/11519 (2013.01); H01L 29/42324 (2013.01);
Abstract

A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.


Find Patent Forward Citations

Han, Liang. (2019). Memory and fabrication method thereof (U.S. Patent No. 10325810). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10325810

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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