The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Dec. 17, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Cheng Wang, SanRamon, CA (US);
Youfeng Wu, Palo Alto, CA (US);
Sara S. Baghsorkhi, San Jose, CA (US);
Albert Hartono, Santa Clara, CA (US);
Robert Valentine, Kiryat Tivon, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/52 (2006.01); G06F 12/0875 (2016.01); G06F 12/0817 (2016.01);
U.S. Cl.
CPC ...
G06F 9/528 (2013.01); G06F 12/0828 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01);
Abstract
Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.