The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Feb. 25, 2015
Applicant:

Toyota Jidosha Kabushiki Kaisha, Toyota-shi, Aichi-ken, JP;

Inventors:

Toru Onishi, Nagoya, JP;

Shuhei Oki, Nagakute, JP;

Tomoharu Ikeda, Nissin, JP;

Rahman Md. Tasbir, Nagoya, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/225 (2006.01); H01L 29/423 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66348 (2013.01); H01L 21/2253 (2013.01); H01L 21/28035 (2013.01); H01L 21/28114 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/739 (2013.01); H01L 29/7397 (2013.01); H01L 29/1608 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01);
Abstract

Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.


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