The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Sep. 19, 2018
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Jeong Soo Byun, Cupertino, CA (US);

Krishnaswamy Ramkumar, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/66 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); B82Y 10/00 (2011.01); H01L 29/06 (2006.01); H01L 29/792 (2006.01); H01L 29/51 (2006.01); H01L 29/16 (2006.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); B82Y 10/00 (2013.01); H01L 21/0223 (2013.01); H01L 21/02164 (2013.01); H01L 21/02252 (2013.01); H01L 21/02323 (2013.01); H01L 21/02326 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/28282 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 22/26 (2013.01); H01L 27/11578 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/16 (2013.01); H01L 29/42344 (2013.01); H01L 29/42364 (2013.01); H01L 29/42392 (2013.01); H01L 29/511 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66439 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.


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