The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Neeraj S. Upasani, Portland, OR (US);

David P. Turley, North Plains, OR (US);

Sergiu D. Ghetie, Hillsboro, OR (US);

Zhangping Chen, Hillsboro, OR (US);

Jason G. Sandri, Gilbert, AZ (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/62 (2013.01); G06F 21/60 (2013.01); G11C 7/24 (2006.01); G11C 7/10 (2006.01); G11C 17/18 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 21/6218 (2013.01); G06F 21/602 (2013.01); G11C 7/1006 (2013.01); G11C 7/24 (2013.01); G11C 17/18 (2013.01); G06F 2221/2107 (2013.01); G11C 29/787 (2013.01);
Abstract

Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.


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