The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Apr. 18, 2012
Applicants:

Sandeep Krishnan, Plainview, NY (US);

Jeffrey Scott Montgomery, Plainview, NY (US);

Lukas Urban, Plainview, NY (US);

Alexander I. Gurary, Plainview, NY (US);

Yuliy Rashkovsky, Plainview, NY (US);

Inventors:

Sandeep Krishnan, Plainview, NY (US);

Jeffrey Scott Montgomery, Plainview, NY (US);

Lukas Urban, Plainview, NY (US);

Alexander I. Gurary, Plainview, NY (US);

Yuliy Rashkovsky, Plainview, NY (US);

Assignee:

Veeco Instruments Inc., Plainview, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/458 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
C23C 16/4584 (2013.01); C23C 16/4583 (2013.01); H01L 21/6875 (2013.01); H01L 21/68714 (2013.01); H01L 21/68728 (2013.01); H01L 21/68735 (2013.01); Y10T 29/49826 (2015.01);
Abstract

A wafer carrier for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition. The wafer carrier includes wafer retention pockets recessed in its body. Each pocket includes a floor surface and a peripheral wall surface surrounding the floor surface and defining a periphery of that pocket. Each pocket has a center situated along a corresponding wafer carrier radial axis. In each of the pockets, a set of bumpers is positioned primarily at a distal portion of the wafer retention pocket opposite the central axis so as to maintain a gap of at least a predefined size between the peripheral wall surface at the distal portion and an edge of a wafer to be placed in the wafer retention pocket.


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