The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Jul. 20, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kensuke Ota, Yokkaichi, JP;

Masumi Saitoh, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2454 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 23/528 (2013.01); H01L 27/249 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2213/15 (2013.01); G11C 2213/32 (2013.01); G11C 2213/52 (2013.01); G11C 2213/71 (2013.01); G11C 2213/75 (2013.01); G11C 2213/79 (2013.01);
Abstract

A semiconductor memory device comprises a substrate, a plurality of first wirings arranged in a first direction crossing a surface of the substrate, a second wiring extending in the first direction, a variable resistance film provided between the first wiring and the second wiring, a third wiring extending in a second direction crossing the first direction, a select transistor provided between an end of the second wiring and the third wiring. In addition, the semiconductor memory device comprises a chalcogen layer provided at at least a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor.


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