The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Nov. 09, 2017
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Wei-Chang Liu, Singapore, SG;

Zhen Chen, Singapore, SG;

Shen-De Wang, Hsinchu County, TW;

Chuan Sun, Singapore, SG;

Wei Ta, Singapore, SG;

Wang Xiang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 27/11521 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/3215 (2006.01); H01L 21/266 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01); H01L 21/266 (2013.01); H01L 21/28273 (2013.01); H01L 21/32155 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.


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