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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10312084 B1

PDFFull Text
Date of Patent:
Jun. 04, 2019

Filed:

Feb. 22, 2017

Semiconductor device and fabrication method thereof

Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuang-Hsiu Chen, Tainan, TW;

Yi-Liang Ye, Kaohsiung, TW;

Chueh-Yang Liu, Tainan, TW;

Yu-Ren Wang, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Attorney:

Winston Hsu

Primary Examiner:

Joseph M Galvin, III

Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 21/033 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/267 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/24 (2006.01); H01L 21/3105 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0335 (2013.01); H01L 21/02521 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/26513 (2013.01); H01L 21/3105 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/0847 (2013.01); H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7848 (2013.01); H01L 21/823871 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

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