The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Jul. 25, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Mario Allegra, Milan, IT;

Mattia Boniardi, Cormano, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/5628 (2013.01); G11C 11/5678 (2013.01); G11C 13/0004 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/141 (2013.01); H01L 45/1675 (2013.01); G11C 2013/009 (2013.01);
Abstract

Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.


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