The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Dec. 08, 2017
Applicants:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Hisanori Aikawa, Seoul, KR;

Tatsuya Kishi, Seongnam-si, KR;

Keisuke Nakatsuka, Seoul, KR;

Satoshi Inaba, Seongnam-si, KR;

Masaru Toko, Seoul, KR;

Keiji Hosotani, Seoul, KR;

Jae Yun Yi, Incheon-si, KR;

Hong Ju Suh, Suwon-si, KR;

Se Dong Kim, Yeoju-si, KR;

Assignees:

TOSHIBA MEMORY CORPORATION, Tokyo, JP;

SK HYNIX INC., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 8/08 (2006.01); G11C 8/12 (2006.01); G11C 13/00 (2006.01); H01L 43/08 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 5/063 (2013.01); G11C 8/08 (2013.01); G11C 8/12 (2013.01); G11C 11/161 (2013.01); G11C 11/1653 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 43/08 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/16 (2013.01); H01L 45/1675 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.


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