The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2019
Filed:
Jan. 22, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
David Baldwin, Weybridge, GB;
Karthik Vaidyanathan, Berkeley, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2011.01); G06T 15/06 (2011.01);
U.S. Cl.
CPC ...
G06T 15/06 (2013.01); G06T 15/005 (2013.01); G06T 2210/12 (2013.01); G06T 2210/21 (2013.01); G06T 2210/36 (2013.01); G06T 2210/61 (2013.01);
Abstract
A level of detail node may hold in a bounding volume hierarchy, an object identifier, a distance at which a transition occurs between levels of detail and a bias. When a level of detail node is encountered in the hierarchy, the distance value may be used to select a level of detail. Sometimes a different level of detail is loaded because the preferred level is not available. The different level may be marked in a register. Then for a subsequence frame, the correct level is used. A node bias may be used to override the level of detail selection is some cases.