The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Jan. 26, 2017
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

John J. Wuu, Fort Collins, CO (US);

Patrick J. Shyvers, Fort Collins, CO (US);

Ryan Alan Selby, Fort Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G11C 7/06 (2006.01); G11C 7/20 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); G11C 7/06 (2013.01); G11C 7/20 (2013.01); G11C 5/025 (2013.01);
Abstract

A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.


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