The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Sep. 25, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Cunming Liang, Shanghai, CN;

Edwin Verplank, Chandler, AZ (US);

David E. Cohen, Hull, MA (US);

Danny Zhou, Shanghai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01); G06F 21/85 (2013.01); G06F 12/0802 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 13/20 (2013.01); G06F 21/85 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.


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