The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Jan. 20, 2018
Applicants:

Triallian Corporation, New Taipei, TW;

Albert Yeh, New Taipei, TW;

Inventors:

Albert Yeh, New Taipei, TW;

Nick Yang, New Taipei, TW;

Assignees:

TRIALLIAN CORPORATION, New Taipei, TW;

Other;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/06 (2006.01); H05K 3/42 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 1/09 (2006.01); H05K 3/26 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H05K 3/06 (2013.01); H05K 1/115 (2013.01); H05K 3/0038 (2013.01); H05K 3/064 (2013.01); H05K 3/424 (2013.01); H05K 3/425 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H05K 1/09 (2013.01); H05K 3/0026 (2013.01); H05K 3/26 (2013.01); H05K 3/4084 (2013.01); H05K 2201/0323 (2013.01); H05K 2201/09509 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/0392 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/0759 (2013.01); H05K 2203/107 (2013.01); H05K 2203/122 (2013.01); Y10T 29/49165 (2015.01);
Abstract

A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 μm is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.


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