The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Dec. 23, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alexander Leckey, Kilcock, IE;

Joseph M. Butler, Stamullen Co Meath, IE;

Thijs Metsch, Cologne, DE;

Giovani Estrada, Dublin, IE;

Vincenzo M. Riccobene, Leixlip, IE;

John M. Kennedy, Clane, IE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/08 (2006.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
H04L 67/1008 (2013.01); H04L 41/5025 (2013.01);
Abstract

One embodiment provides an apparatus. The apparatus includes ranker logic. The ranker logic is to rank each of a plurality of compute nodes in a data center based, at least in part, on a respective node score. Each node score is determined based, at least in part, on a utilization (U), a saturation parameter (S) and a capacity factor (C). The capacity factor is determined based, at least in part, on a sold capacity (C) related to the compute node. The ranker logic is further to select one compute node with a highest node score for placement of a received workload.


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