The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Aug. 10, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lukas Czornomaz, Zurich, CH;

Veeresh V. Deshpande, Zurich, CH;

Vladimir Djara, Kilchberg, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02274 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/32115 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/6656 (2013.01); H01L 29/66522 (2013.01); H01L 29/66628 (2013.01); H01L 29/786 (2013.01); H01L 21/2855 (2013.01); H01L 21/28556 (2013.01);
Abstract

The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.


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