The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Jul. 10, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Clemens Ostermaier, Villach, AT;

Gerhard Prechtl, St. Jakob i. Rosental, AT;

Oliver Häberlen, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/768 (2006.01); H01L 29/778 (2006.01); H01L 29/423 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0607 (2013.01); H01L 21/76879 (2013.01); H01L 29/7786 (2013.01); H01L 29/0657 (2013.01); H01L 29/2003 (2013.01); H01L 29/423 (2013.01);
Abstract

A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.


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