The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Sep. 16, 2013
Applicant:

Ovonyx Memory Technology Llc, Alexandria, VA (US);

Inventor:

Pierre C. Fazan, Lonay, CH;

Assignee:

OVONYX MEMORY TECHNOLOGY, LLC, Alexandria, VA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 27/105 (2006.01); G11C 11/404 (2006.01); H01L 27/108 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 27/115 (2017.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); G11C 11/404 (2013.01); H01L 21/84 (2013.01); H01L 27/108 (2013.01); H01L 27/10802 (2013.01); H01L 27/10844 (2013.01); H01L 27/1203 (2013.01); H01L 29/7841 (2013.01); G11C 2211/4016 (2013.01); H01L 27/115 (2013.01); H01L 29/1608 (2013.01); H01L 29/20 (2013.01); H01L 29/2003 (2013.01);
Abstract

An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.


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