The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Oct. 20, 2015
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

David Trussell, Fremont, CA (US);

Richard Gould, Fremont, CA (US);

John Daugherty, Fremont, CA (US);

Assignee:

LAM RESEARCH CORPORATION, Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/673 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67201 (2013.01); H01L 21/6732 (2013.01); H01L 21/67063 (2013.01); H01L 21/67161 (2013.01); H01L 21/67207 (2013.01); H01L 21/67727 (2013.01); H01L 21/67742 (2013.01); H01L 21/67745 (2013.01); H01L 21/67757 (2013.01); H01L 21/67766 (2013.01);
Abstract

A load lock assembly includes a first load lock connected between an equipment front end module (EFEM) and a wafer transport module, the EFEM being at a lab ambient condition, the wafer transport module being at a vacuum condition, the wafer transport module being part of a wafer transport assembly that is configured to transport wafers to and from one or more process modules that are connected to the wafer transport assembly; a second load lock disposed over the first load lock, the second load lock connected between the EFEM and the wafer transport module; a post-processing module disposed over the second load lock, the post-processing module configured for performing a post-processing operation on a processed wafer that has been processed in at least one of the process modules that are connected to the wafer transport assembly, the post-processing module being configured for connection to the wafer transport module.


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