The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Dec. 18, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventor:

Elliot John Smith, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/66 (2006.01); H01L 21/285 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28052 (2013.01); H01L 21/28518 (2013.01); H01L 22/14 (2013.01); H01L 27/0883 (2013.01); H01L 29/41783 (2013.01); H01L 29/4933 (2013.01); H01L 29/66606 (2013.01);
Abstract

By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors.


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