Memory device and operation method thereof

Abstract

A memory device includes a memory array including a number of memory cell strings, a number of bit lines, a number of pre-charge circuits coupled to the memory cell strings, and a number of sense amplifier circuits coupled to the memory cell strings through the bit lines. Each memory cell string includes at least one first select transistor, a second select transistor and at least one memory cell. Each bit line includes a third select transistor, and is coupled to a memory cell string. During a pre-charging stage, the pre-charge circuits provide a first voltage to pre-charge the memory cell strings. During a programming stage, for the memory cell strings to be inhibited, the sense amplifier circuits provide a second voltage lower than the first voltage. For the memory cell strings to be programmed, the sense amplifier circuits provide a third voltage lower than the second voltage.