The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Apr. 25, 2018
Applicant:

Disco Corporation, Tokyo, JP;

Inventor:

Naotoshi Kirihara, Tokyo, JP;

Assignee:

Disco Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23K 26/00 (2014.01); B23K 26/08 (2014.01); B23K 26/53 (2014.01); H01L 21/78 (2006.01); H01L 33/00 (2010.01); B23K 101/40 (2006.01); B23K 26/382 (2014.01); B23K 26/0622 (2014.01);
U.S. Cl.
CPC ...
H01L 33/005 (2013.01); B23K 26/0006 (2013.01); B23K 26/0622 (2015.10); B23K 26/083 (2013.01); B23K 26/0869 (2013.01); B23K 26/382 (2015.10); B23K 26/53 (2015.10); H01L 21/78 (2013.01); H01L 33/0095 (2013.01); B23K 2101/40 (2018.08);
Abstract

A method of processing a wafer includes applying a laser beam having a wavelength that is transmittable through a sapphire substrate to the wafer while positioning a focused spot of the beam within the wafer in regions corresponding to projected dicing lines through a reverse side of the wafer, thereby forming a plurality of shield tunnels made up of a plurality of pores and an amorphous body surrounding the pores, at predetermined spaced intervals in the wafer along the projected dicing lines. A laser beam having a wavelength that is transmittable through the sapphire substrate to the wafer is applied while positioning a focused spot of the laser beam within the wafer in the projected dicing lines through the reverse side of the wafer, thereby forming modified layers between adjacent shield tunnels. Exerting external forces to the wafer divides the wafer into a plurality of optical device chips.


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