The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Apr. 07, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wan-Chen Chen, Hsinchu, TW;

Yu-Hsiung Wang, Zhubei, TW;

Han-Yu Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 27/11575 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/11573 (2017.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11575 (2013.01); H01L 21/28282 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 28/87 (2013.01); H01L 28/88 (2013.01); H01L 28/91 (2013.01); H01L 29/42344 (2013.01); H01L 29/42352 (2013.01); H01L 29/66181 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/945 (2013.01);
Abstract

The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.


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