The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Sep. 04, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Yuki Noda, Yokkaichi Mie, JP;

Ippei Kume, Yokkaichi Mie, JP;

Kazuhiko Nakamura, Nagoya Aichi, JP;

Koichi Sato, Oita Oita, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/302 (2006.01); H01L 21/311 (2006.01); H01L 21/283 (2006.01); H01L 23/52 (2006.01); H01L 21/768 (2006.01); H01L 21/3065 (2006.01); H01L 23/528 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/308 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/02126 (2013.01); H01L 21/288 (2013.01); H01L 21/2885 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76841 (2013.01); H01L 21/76873 (2013.01); H01L 21/76874 (2013.01); H01L 21/76879 (2013.01); H01L 21/76898 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53209 (2013.01); H01L 24/13 (2013.01); H01L 2224/13025 (2013.01);
Abstract

A method of producing a semiconductor device includes forming, on a semiconductor substrate comprising a first surface on which an insulating layer covering a wiring structure and a first through via passing through the insulating layer are formed and a second surface opposed to, and facing away from, the first surface, a patterned first insulating film comprising at least one opening therethrough on the second surface, forming a through via hole inwardly of the second surface within which the wiring structure is exposed, by anisotropic dry etching into the second surface side of the semiconductor substrate through the at least one opening in the first insulating film, using a gas mixture containing SF, O, SiF, and at least one of CF, Cl, BCl, CFI, and HBr, and forming a second through via in the through via hole.


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