The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Jun. 09, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debendra Das Sharma, Saratoga, CA (US);

Mohan J. Kumar, Aloha, OR (US);

Balint Fleischer, Groton, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 9/52 (2006.01); G06F 3/06 (2006.01); G06F 11/20 (2006.01); G06F 13/32 (2006.01); G06F 12/0815 (2016.01); G06F 9/46 (2006.01); G06F 12/1081 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 14/00 (2006.01); G06F 12/0817 (2016.01);
U.S. Cl.
CPC ...
G06F 9/52 (2013.01); G06F 3/0619 (2013.01); G06F 3/0661 (2013.01); G06F 3/0688 (2013.01); G06F 9/467 (2013.01); G06F 11/2017 (2013.01); G06F 12/0815 (2013.01); G06F 12/1081 (2013.01); G06F 13/1663 (2013.01); G06F 13/32 (2013.01); G06F 13/4022 (2013.01); G11C 14/009 (2013.01); G06F 12/0817 (2013.01); G06F 2212/1056 (2013.01);
Abstract

An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.


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